Multiple mask step and scan aligner

ABSTRACT

A new optical lithographic exposure apparatus is described. The apparatus may comprise, for example, a lithographic stepper or scanner. A wafer stage comprises a means of supporting a semiconductor wafer. A mask stage comprises a means of holding a first mask and a second mask and maintaining a fixed relative position between the first mask and the second mask. The mask stage may further comprise an independent means of aligning each mask. A light source comprises a means to selectively shine actinic light through one of the first mask and the second mask. An imaging lens is capable of focusing the actinic light onto the semiconductor wafer. A step and scan method using the mask stage is provided. A first mask and a second mask are loaded into a mask stage of an optical lithographic exposure apparatus. The first mask and the second mask are aligned. The first mask is scanned. The wafer is then stepped. The second mask is scanned. By repeating this sequence across the wafer twice, the patterns of the first mask and the second mask are thereby superimposed in every field. The photoresist layer is developed to thereby create the patterning in the manufacture of the integrated circuit device.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The invention relates to a method of fabricating semiconductorstructures, and more particularly, to an optical lithographic exposureapparatus with a multiple mask capability suitable for double-exposureprocesses in the manufacture of integrated circuits.

(2) Description of the Prior Art

As optical lithography is used to delineate 0.1 micron and smallerfeatures, the lithographic tools must work in a low k₁ region. The k₁,or Rayleigh's coefficient, for resolution, is given by the equation:$k_{1} = \frac{{CD} \times {NA}}{\lambda}$where CD is the critical dimension of the line feature, NA is thenumerical aperture, and λ is the wavelength of the exposure light. Forexample, if the exposure wavelength is 193 nanometers and the NA is0.63, then k₁ is 0.39. At such a low k₁, extremely aggressive imageenhancing techniques have to be used to produce usable images for ICmanufacture. One such technique is the use of double exposures with twodifferent masks.

For example, an alternating phase shifting mask (PSM) may be used whenthe desired feature size of an integrated circuit layer is on the sameorder of magnitude as the wavelength of light used in thephotolithographic process. If a PSM is used, then a second exposure froma binary intensity mask (BIM) must be performed to remove any extralines caused by the phase shifting interference at the featureboundaries.

In a typical photolithographic mask, layer features, or traces, areformed on the mask in an opaque material such as chrome. This chromelayer is formed overlying a transparent quartz substrate. Light is shownthrough this mask to expose a photosensitive material, commonlyphotoresist, as defined by the mask pattern. After the photoresist isdeveloped, the photoresist will reflect a copy or a reverse copy of themask pattern.

However, in a phase shifting mask, an additional component is added tothe chrome and quartz system. Either through the application of anadditional transparent layer or the through the removal of a portion ofthe quartz layer to a specific depth, the optical properties are changedin a part of the transparent (not covered by chrome) sections of themask. Specifically, when light of the lithographic wavelength is shownthrough the mask, a phase shift is created between light waves that passthrough the phase shifted area and the light waves that pass through thenon-phase shifted area. By shifting the phase of the light by 180degrees, nodes, or cancellations of energy will occur at opaqueboundaries between the phase shifted and non-phase shifted areas. Thisprinciple is used to create more sharply defined boundary conditionsduring the photolithographic exposure. Sharper definition leads toimproved pattern transfer.

In the case of the PSM method, two distinct reticles, the phase shiftingmask (BIM) and binary intensity mask (BIM) are used. Referring now toFIG. 1, an alternating PSM mask 10 is shown for a simple feature. Achrome line 14 is formed on the mask. The chrome 14 is opaque andreflects exposure light away from the semiconductor wafer. Thetransparent regions of the mask 10 are divided into a zero degree, ornon-phase shifting, region 18 and a 180 degree, or phase shifting,region 22. The phase shifting region 22 is specially treated to causethe transmitted exposure light to be shifted 180 degrees with respect totransmitted exposure light traveling through the non-phase shiftingregion 18.

Referring now to FIG. 2, the BIM mask 30 is illustrated. The purpose ofthe BIM mask 30 is to remove any extra lines caused by the interferenceof the phase shifted light and non-phase shifted light at the boundariesof each region. The BIM mask 30 contains a chrome feature 34 overlyingthe transparent substrate 38. The feature 34 is an appropriatelyoversized copy of the critical PSM feature of the PSM mask.

The PSM mask and the BIM mask are used sequentially. First, thesemiconductor wafer is coated with a photoresist layer. Second, the PSMmask of FIG. 1 is loaded into the mask stage of the optical lithographicstepper and aligned. The photoresist layer is then exposed, field byfield, to actinic light through the PSM mask. Third, the PSM mask isreplaced with the BIM mask of FIG. 2. The BIM mask must be aligned. Theundeveloped photoresist layer is exposed, field-by-field, to actiniclight through the BIM layer. At the end of the process, every field hasbeen exposed to thereby superimpose the patterns of the PSM mask and theBIM mask in every field.

Referring now to FIG. 3, a top view of the semiconductor substrate isshown. The photoresist layer 54 is developed. The photoresist layer 54exhibits a very defined pattern overlying the semiconductor substrate50. The double-exposure method enables the creation of smaller linewidths than possible with a single, non-phase shifted exposure.

If a conventional stepper is used for this process, the operator mustfirst install and then align the first mask. After exposing through thefirst mask, the operator must remove the first mask and install thesecond mask. This is because the conventional stepper can only hold andalign a single mask at a time. The second mask must be aligned prior tothe second exposure. It would be very advantageous and cost saving toeliminate a reticle change and alignment from the double-exposureprocess.

Several prior art approaches concern methods to double-expose anintegrated circuit and apparatus for holding masks. U.S. Pat. No.5,989,761 to Kawakubo et al teaches a method to expose photolithographicmasks onto a substrate. First and second masks, corresponding todifferent substrate layers, are used. The first and second masks areexposed with different apparatus having different exposure field sizes.The first mask is exposed on the first apparatus. A perpendicular errorand a mean value of rotation are detected for the first exposure. Thesecond mask is rotated based on the detected error of the first mask tocompensate and correct the error. U.S. Pat. No. 5,847,813 to Hirayanagidiscloses a mask holding apparatus for lithographic exposure masks. Theapparatus adds an inner frame to the conventional outer frame to therebyimprove support, thermal transfer, and electrical grounding. U.S. Pat.No. 4,924,258 to Tsutsui teaches a mask holding and conveying mechanism.The mask holding mechanism comprises a reference member, an aperture, aspring-biased first member, and a spring-biased second member.

SUMMARY OF THE INVENTION

A principal object of the present invention is to provide an effectiveoptical lithographic exposure apparatus and method of use thereof forpatterning a photoresist layer in the manufacture of an integratedcircuit device.

A further object of the present invention is to provide an exposureapparatus capable of holding two masks in a fixed relative position forsequential exposure of the mask patterns onto a semiconductor wafer.

A yet further object of the present invention is to provide an exposureapparatus capable of aligning two masks prior to the sequential exposureof the mask patterns onto a semiconductor wafer to thereby save time.

Another yet further object of the present invention is to provide anexposure apparatus capable of independently aligning two masks.

Another further object of the present invention is to provide aneffective and very manufacturable method to pattern a photoresist layerwherein the photoresist layer is sequentially exposed to actinic lightthrough two different masks.

Another yet further object of the present invention is to use a two maskholding apparatus to sequentially expose the photoresist layer through aPSM mask and through a BIM mask to thereby enhance the image of thepattern.

Another yet further object of the present invention is to exposesequentially the photoresist layer through the first mask and the secondmask without a mask change and alignment to thereby save time.

In accordance with the objects of this invention, a new opticallithographic exposure apparatus is described. The apparatus may comprisestep and scan capability. A wafer stage comprises a means of supportinga semiconductor wafer. A mask stage comprises a means of holding a firstmask and a second mask and maintaining a fixed relative position betweenthe first mask and the second mask. The mask stage may further comprisean independent means of aligning each mask. A light source comprises ameans to selectively shine actinic light through either the first maskor the second mask. An imaging lens is capable of focusing the actiniclight onto the semiconductor wafer. A means of stepping the mask stageacross the semiconductor wafer is provided.

Also in accordance with the objects of the present invention, a newmethod to pattern a photoresist layer in the manufacture of anintegrated circuit device is achieved. A photoresist layer is depositedoverlying a semiconductor substrate. A first mask and a second mask areloaded into a mask stage of an optical lithographic exposure apparatushaving a step and scan capability. The mask stage maintains a fixedrelative position between the first mask and the second mask. The firstmask and the second mask are aligned. The wafer is indexed to a startingfield that becomes the current field. The first mask is scanned toexpose the current field. The wafer is then indexed to a next fieldunexposed by the first mask. The stepping and scanning is repeated untilevery field on the semiconductor substrate is exposed with the firstmask. The wafer is then indexed to the starting field that becomes thecurrent field. The second mask is scanned to expose the current field.The wafer is then indexed to a next field unexposed by the second mask.The stepping and scanning is repeated until every field on thesemiconductor substrate is exposed with the second mask. The patterns ofthe first mask and the second mask are thereby superimposed in everyfield. The photoresist layer is developed to thereby complete thepatterning in the manufacture of the integrated circuit device.

Also in accordance with the objects of the present invention, a newmethod to pattern a photoresist layer in the manufacture of anintegrated circuit device is achieved. A photoresist layer is depositedoverlying a semiconductor substrate. A first mask and a second mask areloaded into a mask stage of an optical lithographic exposure apparatushaving a step and scan capability. The mask stage maintains a fixedrelative position between the first mask and the second mask. The firstmask and the second mask are aligned. The wafer is indexed to a startingfield that becomes the current field. The first mask is scanned toexpose the current field. The second mask is scanned to expose theadjacent field. The wafer is stepped to a next field unexposed by thefirst mask. The stepping and scanning is repeated until every field onthe semiconductor substrate is exposed. The wafer is indexed to thestarting field. The wafer is then stepped to a next field unexposed bythe second mask to become the current field. The second mask is scannedto expose the current field. The wafer is then indexed to the next fieldunexposed by the first mask to become the current field. The first maskis scanned to expose the current field. The stepping and scanning isrepeated until every field on the semiconductor substrate is exposed.The patterns of the first mask and the second mask are therebysuperimposed in every field. The photoresist layer is developed tothereby complete the patterning in the manufacture of the integratedcircuit device.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings forming a material part of thisdescription, there is shown:

FIG. 1 illustrates in simplified form an alternating phase shifting mask(PSM).

FIG. 2 illustrates in simplified form a binary intensity mask (BIM).

FIG. 3 illustrates in simplified form a photoresist feature formed bydouble-exposure using the PSM mask of FIG. 1 and the BIM mask of FIG. 2.

FIG. 4 illustrates in simplified form the key components of thepreferred embodiment of the optical stepper apparatus of the presentinvention.

FIGS. 5 and 6 illustrate two configurations of a mask stage for thepreferred embodiment apparatus of the present invention.

FIG. 7 illustrates the optional addition of a viewing microscope withalignment marks to the apparatus of the present invention.

FIG. 8 illustrates, in flow chart form, a first preferred embodiment ofthe method of the present invention.

FIGS. 9 and 10 illustrate a semiconductor wafer processed by the firstpreferred embodiment of the method of the present invention.

FIG. 11 illustrates, in flow chart form, a second preferred embodimentof the method of the present invention.

FIGS. 12 through 14 illustrate a semiconductor wafer processed by thesecond preferred embodiment of the method of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The embodiments disclose an optical lithographic exposure apparatus witha novel mask stage capable of holding and aligning two masks at a time.This apparatus may comprise, for example, an optical stepper or scanner.Further, it is preferred that the exposure apparatus have a step andscan capability. This apparatus is ideally suited for double-exposureprocessing in the manufacture of an integrated circuit device. Inaddition, two methods for double exposing using a two-mask step and scanprocess are described. It should be clear to those experienced in theart that the present invention can be applied and extended withoutdeviating from the scope of the present invention.

Referring now particularly to FIG. 4, a simplified form of the preferredembodiment of the apparatus of the present invention illustrated. Thekey components of a new optical lithographic exposure apparatus areshown. This apparatus adds the ability to load and align two masks andthen expose a semiconductor wafer using each of these reticles without atime consuming mask change and alignment step. The semiconductor wafer274 is supported on a wafer stage 276.

An important aspect of the present invention is the novel mask stage250. This mask stage 250 comprises a means of holding a first mask 262and a second mask 260. Each mask 260 and 262 is held in a separatefixture 256 and 258 in the mask stage 250. Each mask 260 and 262 can beindependently aligned to the wafer 274 and to the other mask. Oncealigned, the mask stage 250 maintains the fixed relative positionbetween the first mask 262 and the second mask 262.

The ability to independently hold and align the two masks 260 and 262allows an operator to load both masks at the beginning of thelithographic operation. Both masks 260 and 262 are then aligned. Eachmask can then be used for exposing fields on the semiconductor wafer 272without a time consuming mask change therebetween.

A light source 254 comprises a means of selectively shining actiniclight through either the first mask 262 or the second mask 260. Thelight source 254 may comprise, for example, a laser-based source with aspecific light wavelength. In the preferred embodiment, the light source254 comprises a wavelength of 193 nanometers. The light source 254 mayinclude an optical circuit capable of flashing the actinic light for aspecific length of time.

An imaging lens 270 is capable of focusing the actinic light that passesthrough either of the masks 260 and 262 onto the semiconductor wafer274. The imaging lens 270 and the mask stage 250 are linked such thatthe image of the exposed mask will be focused onto a particular field ofthe wafer 274 during each exposure step. Further, the imaging lens 270and the mask stage 250 can be stepped, or indexed, from field to fieldacross the semiconductor wafer.

The preferred application of the stepper apparatus having a two-maskstage 250 is the double-exposure process described in FIGS. 1 through 3.For example, an alternating PSM mask of the type shown in FIG. 1 may beloaded into the first mask fixture 258. A binary intensity mask (BIM) ofthe type shown in FIG. 2 may be loaded into the second mask fixture 256.Both masks 260 and 262 are then aligned. The apparatus may then be usedto sequentially expose every field on the semiconductor wafer to actiniclight through both the PSM mask 262 and the BIM mask 260 such that thepatterns of each mask are superimposed on each field. The novel abilityto hold two masks, to maintain a fixed relational position between thetwo masks, and to align both masks prior to exposure provides asignificant flexibility and time savings for the operator.

Referring briefly now to FIG. 9, a semiconductor wafer 400 isillustrated. An array of fields 404 is shown. The exposure apparatus ofthe present invention exposes single fields 404 across the wafer. Whenfields are completed, the stepper indexes to the next field until theentire wafer is exposed. Each field may comprise several integratedcircuit die. The preferred embodiment exposure apparatus comprises astep and scan capability. Step and scan uses an illuminated slot whichis scanned over the mask to expose the wafer. While the lens remainsstationary, the mask and wafer move in a controlled fashion. The waferis stepped to a field and then the mask is scanned. In a 4× system, forexample, the mask moves 4 times faster than the wafer.

Returning now to FIG. 4, note that the scanning direction of theapparatus is shown. In this embodiment, the novel mask stage 250 isconfigured such that the first mask 262 and the second mask 260 areplaced side-by-side in the same direction as the scanning direction.Alternatively, the first mask and second mask may be configured acrossthe scanning direction.

Referring now to FIG. 5, one such configuration of the mask stage isshown in greater detail. Several important features of the presentinvention are shown. In this configuration, the mask stage 100 isconfigured such that the fixed relative position between the first mask104 and the second mask 108 is consistent with the scanning direction.Further, the first mask 104 and the second mask 108 are adjacent to eachother and in the same plane (coplanar).

Each wafer fixture 112 and 116 in the mask stage 100 has a set ofindependent alignment controls. The first fixture 112 may have an ‘x’lateral control 124 and a ‘y’ lateral control 120, or both. Similarly,the second fixture 116 may have an ‘x’ lateral control 132 and a ‘y’lateral control 128, or both. In addition, the first fixture 112 and thesecond fixture 116 may have angular controls 126 and 134 to adjust theangle of placement (θ) of each mask. The alignment controls are used tocarefully align the mask alignment marks 144 and 148 on the masks 104and 108 with the wafer alignment marks. These alignment controls maycomprise mechanical actuators or electromechanical actuators. Oncealigned, the mask stage 100 maintains alignment.

Referring now to FIG. 6, the mask stage 100 is shown in a secondscanning configuration. In this configuration, the mask stage 100 isconfigured such that the fixed relative position between the first mask104 and the second mask 108 is perpendicular with the scanningdirection. Again, the first mask 104 and the second mask 108 areadjacent to each other and in the same plane (coplanar).

Referring now to FIG. 7, an optional feature of the present invention isillustrated. A microscope viewer 216 provides a complimentary alignmentand viewing means for the operator. The operator uses the microscopeview 216 to register the alignment marks 208 and 212 on the masks 200and 204 with complimentary alignment marks on the microscope objectives.This enables an off-axis alignment mechanism for the operator.

The two-mask stage of the present invention may be extended to amultiple mask stage by adding an additional mask fixture and alignmentsystem. In this case, the first mask, second mask, and additional maskwould be held in a fixed relative position after alignment to facilitatea sequential exposure of a wafer using each mask.

Referring now to FIG. 8, a first preferred embodiment of a method topattern a photoresist layer in the manufacture of an integrated circuitdevice is shown. This method uses the novel two-mask stage of theapparatus of the present invention to improve the double-exposurescenario outlined in FIGS. 1 through 3. First, a photoresist layer isdeposited overlying a semiconductor substrate in step 500. The firstmask and the second mask are loaded into the novel two-mask stage instep 504. Note that, in this first embodiment of the double-exposuremethod, either the consistent (FIG. 5) or the perpendicular (FIG. 6)mask configuration may be used. The first mask and the second mask arealigned in step 508.

The first mask scan is now performed. First, the wafer is indexed to thestarting field to set the current field location in step 512. Referringto FIG. 9, the starting field 406 is the uppermost, left-side field ofthe wafer. Referring again to FIG. 8, the first mask is scanned toexpose the current field in step 516. The wafer is then stepped to thenext field unexposed by the first mask to set a new current field instep 520. The scanning (step 516) and stepping (step 520) are repeateduntil all the fields on the wafer are exposed.

Referring once again to FIG. 9, a top view of the semiconductor wafer400 is shown at the end of step 520. Every field 404 in the wafer hasbeen exposed through the first mask at this point in the method.

Referring once again to FIG. 8, the second mask scan is now performed.The wafer is returned to the starting field 406 (in FIG. 9) to set thecurrent field in step 524. The second mask is scanned to expose thecurrent field in step 528. The wafer is then stepped to the next fieldunexposed by the second mask to set a new current field in step 532. Thescanning (step 528) and stepping (step 532) are repeated until all thefields on the wafer are exposed.

Referring now to FIG. 10, the semiconductor wafer 400 is shown at theend of step 532. Every field 404 has now been exposed through the secondmask. Now, the pattern of the first mask and the second mask issuperimposed on every field 404 of the wafer 400.

Referring once again to FIG. 8, the photoresist layer is developed tocomplete the method of patterning in step 536.

Referring now to FIG. 11, a second preferred embodiment of a method topattern a photoresist layer in the manufacture of an integrated circuitdevice is shown. This method again uses the novel two-mask stage of theapparatus of the present invention to improve the double-exposurescenario outlined in FIGS. 1 through 3. First, a photoresist layer isdeposited overlying a semiconductor substrate in step 600. The firstmask and the second mask are loaded into the novel two-mask stage instep 604. Note that, in this second embodiment of the double-exposuremethod, only the consistent (FIG. 5) mask configuration may be used. Thefirst mask and the second mask are aligned in step 608.

The wafer is indexed to the starting field to set the current field instep 612. Referring to FIG. 12, the starting field 306 is the uppermost,left-side field of the wafer. Referring again to FIG. 11, the first maskis scanned to expose the current field in step 616. Next, the secondmask is scanned to expose the adjacent field in step 620. Note that itis not necessary to step the mask stage to do this exposure since thesecond mask is held adjacent to the first mask and is already positionedto expose the field adjacent to the field exposed through the firstmask. The wafer is now stepped to the next field unexposed by the firstmask to set a new current field in step 624. The scanning (step 616 andstep 620) and stepping (step 624) are repeated until all the fields onthe wafer are exposed.

Referring once again to FIG. 12, a top view of the semiconductor wafer300 is shown at the end of step 624. Every field on the wafer has beenexposed through either the first mask 304 or the second mask 308 duringthis first pass scan.

Referring once again to FIG. 11, the second pass scan is now performed.The wafer is returned to the starting field 306 (in FIG. 12) to set thecurrent field in step 628. The wafer is stepped to the next fieldunexposed by the second mask to set a new current field. Referring nowto FIG. 13, the next field unexposed by the second mask 309 is shown.The second mask is scanned to expose the current field in step 636. Thewafer is then stepped to the next field unexposed by the first mask toset a new current field in step 640. The first mask is now scanned toexposed the current field in step 644. The scanning (step 636 and step644) and stepping (step 640) are repeated until all the fields on thewafer are exposed.

Referring again to FIG. 13, the semiconductor wafer 300 is shown at theend of step 644. Now, the pattern of the first mask and the second maskis superimposed on every field 304 and 308 of the wafer 300. Note thatonly single mask scans are required at the beginning and ending fields312 of each row. These single mask exposure fields are called fill-infields 312.

Referring now to FIG. 14, the fill-in fields may be completed using apartial scan wherein the stepper is programmed to single expose thebeginning and ending fields 312 with the missing mask.

Referring once again to FIG. 11, the photoresist layer is developed tocomplete the method of patterning in step 648.

The optical lithographic exposure apparatus described provides asignificant advantage over the prior art. The novel two-mask stageenables a double-exposure process without a time consuming mask changeand alignment. This facilitates the use of alternating phase shiftingmask (PSM) technology to produce very fine line width features in anintegrated circuit manufacturing process. The methods of patterning aphotoresist layer using the two-mask stage provide a very manufacturableapproach to phase shifting mask lithography.

While the invention has been particularly shown and described withreference to the preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade without departing from the spirit and scope of the invention.

1-27. (Canceled).
 28. A method of arranging masks, comprising: holding afirst mask and a second mask; and maintaining a fixed relative positionbetween the first mask and the second mask.
 29. The method as claimed inclaim 28, wherein the first mask and the second mask are placed side byside.
 30. The method as claimed in claim 28, wherein the first mask andthe second mask are placed side by side in a same direction as ascanning direction.
 31. The method as claimed in claim 28, wherein thefirst mask and the second mask are configured across a scanningdirection.
 32. The method as claimed in claim 28, wherein the first maskand the second mask are held in a separate fixture of a mask stage. 33.The method as claimed in claim 28, wherein the first mask comprises aphase-shifting mask.
 34. The method as claimed in claim 28, wherein thesecond mask comprises a binary intensity mask.
 35. A method forpatterning a photoresist layer, comprising: depositing a photoresistlayer overlying a wafer; exposing the photoresist layer with a pluralityof masks held in a mask stage, wherein the mask stage maintains a fixedrelative position between each two adjacent masks; and developing thephotoresist layer.
 36. The method as claimed in claim 35, wherein thesteps of exposing the photoresist layer with the plurality of masks heldin a mask stage comprise: loading the mask stage holding the pluralityof masks; aligning the plurality of masks; and scanning the plurality ofmasks and stepping the wafer to expose the photoresist layer with eachof the plurality of masks respectively.
 37. The method as claimed inclaim 36, wherein the plurality of masks are aligned prior to anyexposing and stepping.
 38. The method as claimed in claim 35, whereinthe plurality of masks are placed side by side in a same direction as ascanning direction.
 39. The method as claimed in claim 35, wherein theplurality of masks are placed side by side and configured across ascanning direction.
 40. The method as claimed in claim 35, wherein theplurality of masks are held in a separate fixture of a mask stage. 41.The method as claimed in claim 35, wherein the first mask and the secondmask are held in a separate fixture of a mask stage.
 42. A method forpatterning a photoresist layer, comprising: depositing a photoresistlayer overlying a wafer comprising a plurality of fields; exposing thephotoresist layer with a first mask and a second mask both held in amask stage, wherein the mask stage maintains a fixed relative positionbetween the first mask and the second mask; and developing thephotoresist layer.
 43. The method as claimed in claim 42, wherein thesteps of exposing the photoresist layer with the first mask and thesecond mask held in a mask stage comprise: loading the mask stageholding the first mask and the second mask; aligning the first mask andthe second mask; and scanning the first mask and stepping the wafer toexpose each of fields; and scanning the second mask and stepping thewafer to expose each of fields.
 44. The method as claimed in claim 43,wherein the first mask and the second mask are placed side by side in asame direction as a scanning direction.
 45. The method as claimed inclaim 43, wherein the first mask and the second mask are placed side byside and configured across a scanning direction.
 46. The method asclaimed in claim 43, wherein first mask comprises a phase-shifting maskand wherein the second mask comprises a binary intensity mask.
 47. Themethod as claimed in claim 43, wherein the first mask and the secondmask are held in a separate fixture of the mask stage.
 48. The method asclaimed in claim 42, wherein the steps of exposing the photoresist layerwith the first mask and the second mask held in a mask stage comprise:loading the mask stage holding the first mask and the second mask;aligning the first mask and the second mask; and scanning the first maskto expose a first field; scanning the second mask to expose a secondfield adjacent to the first field; stepping the wafer and repeating thescanning steps until each of fields is exposed with the first mask andthe second mask.
 49. The method as claimed in claim 48, wherein thefirst mask and the second mask are placed side by side in a samedirection as a scanning direction.
 50. The method as claimed in claim48, wherein the first mask and the second mask are placed side by sideand configured across a scanning direction.
 51. The method as claimed inclaim 48, wherein first mask comprises a phase-shifting mask and whereinthe second mask comprises a binary intensity mask.
 52. The method asclaimed in claim 48, wherein the first mask and the second mask are heldin a separate fixture of the mask stage.
 53. A method for fabricating anintegrated circuit device, comprising: depositing a photoresist layeroverlying a substrate; exposing the photoresist layer with a first maskand a second mask both held in a mask stage, wherein the mask stagemaintains a fixed relative position between the first mask and thesecond mask; developing the photoresist layer to form a photoresistpattern; and patterning the substrate with the photoresist pattern. 54.The method as claimed in claim 53, wherein the first mask and the secondmask are placed side by side.
 55. The method as claimed in claim 53,wherein the first mask and the second mask are placed side by side in asame direction as a scanning direction.
 56. The method as claimed inclaim 53, wherein the first mask and the second mask are configuredacross a scanning direction.
 57. The method as claimed in claim 53,wherein the first mask and the second mask are held in a separatefixture of a mask stage.
 58. The method as claimed in claim 53, whereinthe first mask comprises a phase-shifting mask.
 59. The method asclaimed in claim 53, wherein the second mask comprises a binaryintensity mask.